A semiconductor device manufactured by a method wherein, when the opposite electrode terminals of a substrate and a semiconductor chip mounted on the substrate are connected by solder bumps and a vacant space around said solder bumps is coated with resin, the resin fills up space around the semiconductor chip, so that it is substantially equal in height to the top surface of the semiconductor chip and has a flat surface, is known publicly.
This semiconductor device is disclosed, for instance, in Japanese Pat. Laid-Open No. 107,641/1983 titled "Sealing Method of Semiconductor Device", which was laid open on June 27, 1983.
When a large silicon chip having a side of 8 to 10 mm is fitted on an Al.sub.2 O.sub.3 substrate, in a prior-art semiconductor chip, the difference between the thermal expansion coefficient (.alpha.=2.7.times.10.sup.-6 /.degree.C.) of Si and the coefficient of thermal expansion (.alpha.=6.8.times.10.sup.-6 /.degree.C.) of Al.sub.2 O.sub.3 and the distance between bumps located in the outermost peripheries determine the thermal fatigue service life of solder bumps in a package. A service life of fifteen years is demanded in terms of the distance between the bumps located in the outermost peripheries under severe conditions. A multilayer substrate having a coefficient of thermal expansion of .alpha.=4.times.10.sup.-6 /.degree.C. is required to ensure a service life of fifteen years for an Si chip having a side of 8 to 10 mm, for instance, in order to meet the strong demand for a large, multi-terminal chip. Accordingly, when the Al.sub.2 O.sub.3 substrate is used, it is thought impossible to form solder bumps on the whole surface of the large-sized chip having a side of 8 to 10 mm.
The prior-art semiconductor device has only a thermal fatigue resistance of the same level as a module structure in which bare chips are mounted.